Thursday, June 12, 2014

Toshiba’s new MRAM cache could reduce CPU power consumption by 60%

That would be lovely

You probably don’t spend a lot of time worrying about how efficiently the CPUs in your devices are caching data, but it keeps computer science researchers up at night. Caching is one of the few places we can realize significant power savings with the right tweaks, and that’s increasingly important as mobile devices continue to demand more juice. Toshiba says it has taken a big step in that direction by coming up with a new design for STT-MRAM (spin-transfer torque magnetoresistive random access memory). By replacing the traditional SRAM-based L2 cache on a processor with STT-MRAM, Toshiba believes CPU power consumption can be reduced by a whopping 60%.

Your CPU’s cache is used to store bits of information for faster access, preventing the CPU from needing to reach out to the main system memory for every little thing. Most modern chips have multilevel caches (i.e. L1, L2, and L3), but Toshiba focused on replacing the L2 cache with this new type of MRAM. L2 was the best target because it’s large enough to make a difference in performance, but small enough to still be fast.

SRAM is a type of volatile memory, meaning the data goes away when it’s turned off. MRAM, by contrast, is non-volatile thanks to its vastly different architecture. Whereas all DRAM stores data as units of electric charge, MRAM uses a series of magnetic storage elements. The specific spin-transfer torque version of the technology used by Toshiba uses spin-aligned electrons to modify data more efficiently. According to Toshiba, its MRAM solution could eliminate most of the power leakage from L2 cache, which by itself can account for up to 80% of L2 power usage.

Past efforts to make MRAM work in any practical sense have fallen flat because it simply wasn’t very fast. When designing circuits that increased speeds to an acceptable level, the current leak actually made it less efficient than standard SRAM — that’d hardly be worth using. To make its design work, Toshiba created a new circuit structure that borrows elements from DRAM and SRAM to speed up operation without leaking power. Toshiba claims read times of 4.1 nanoseconds and write times of 2.1 nanoseconds, both very close to SRAM.

This is the sort of low-level hardware feature that will show up in future processor designs without much fanfare, but it might be the key to the next big jump in power efficiency. Toshiba sees this technology as a perfect fit for mobile chips that are quickly growing larger desktop-like caches. Of course, power efficiency is of vital importance in a mobile device, making it worth all this time and effort developing STT-MRAM.

So you might buy a device in the future with STT-MRAM cache without even knowing it, but that’s just the start. Engineers have also been looking at MRAM as a type of potential “universal memory.” It has the potential to take on the roles currently filled by SRAM, as well all those gigabytes of DRAM and terabytes of flash memory storage in your computer. That’s still a long way off (if it works at all), but maybe Toshiba is taking the first step (and funnily enough, HP also announced today that it’s taking the next step with its next “universal memory,” memristors!)

Source: Extremetech

The Chief Technomancer
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